sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 372

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Inter-Integrated Circuit (IICV3) Block Description
Note:Since the bus frequency is speeding up,the SCL Divider could be expanded by it.Therefore,in the
table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is
the divider under the low frequency.Value2 is the divider under the high frequency.How to select the
divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed.
10.3.1.3
Read and write anytime
372
Reset
W
R
IBC[7:0]
Module Base + 0x0002
(hex)
BA
BB
BC
BD
BE
BF
B2
B3
B4
B5
B6
B7
B8
B9
IBEN
IIC Control Register (IBCR)
0
7
= Unimplemented or Reserved
IBIE
0
6
Table 10-7. IIC Divider and Hold Values (Sheet 6 of 6)
SCL Divider
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
(clocks)
Figure 10-6. IIC Bus Control Register (IBCR)
10240
12288
15360
3584
4096
4608
5120
6144
7680
5120
6144
7168
8192
9216
MS/SL
0
5
Tx/Rx
0
4
SDA Hold
(clocks)
1028
1028
1028
1028
1540
1540
2052
2052
516
516
772
772
516
516
TXAK
0
3
SCL Hold
(start)
RSTA
1784
2040
2296
2552
3064
3832
2552
3064
3576
4088
4600
5112
6136
7672
0
0
2
Freescale Semiconductor
0
0
1
SCL Hold
(stop)
1796
2052
2308
2564
3076
3844
2564
3076
3588
4100
4612
5124
6148
7684
IBSWAI
0
0

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