sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 195

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

6.3.2.7.1
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in
the comparator enable bit in the associated DBGXCTL control register.
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State1, based upon the match event.
0
0
7
Debug State Control Register 1 (DBGSCR1)
= Unimplemented or Reserved
Figure 6-9. Debug State Control Register 1 (DBGSCR1)
0
0
6
Table 6-36
Figure 6-1
Table 6-16. State1 Sequencer Next State Selection
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Either Match0 or Match2 to Final State........Match1 to State2
Table 6-15. DBGSCR1 Field Descriptions
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
and described in 6.3.2.8.1. Comparators must be enabled by setting
Match1 to State3.........Match0 to Final State
Match0 to State2....... Match1 to State3
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
Any match to Final State
0
0
4
Match2 to State2
Match1 to State2
Match1 to State3
Match0 to State3
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SC3
0
3
SC2
0
2
S12S Debug Module (S12SDBGV2)
SC1
0
1
SC0
0
0
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