sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 540

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

32 KByte Flash Module (S12FTMRC32K1V1)
The next sections describe:
15.4.3.1
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz.
values for the FDIV field based on BUSCLK frequency.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
15.4.3.2
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
15.4.3.2.1
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
540
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How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
BUSCLK for Flash program and erase command operations
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution
15.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
Section
Writing the FCLKDIV Register
Command Write Sequence
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
Define FCCOB Contents
15.3.2.3).
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
CAUTION
NOTE
Table 15-7
shows recommended
Freescale Semiconductor