sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 361

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10
Inter-Integrated Circuit (IICV3) Block Description
10.1
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of
connections between devices, and eliminates the need for an address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
10.1.1
The IIC module has the following key features:
Freescale Semiconductor
Rev. 1.04
Revision
Number
V01.03
V01.04
•
•
•
•
•
•
•
•
•
Compatible with I2C bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated start signal generation
Introduction
Revision Date
Features
17 Nov 2006
14 Aug 2007
28 Jul 2006
10.7.1.7/10-385
10.3.1.2/10-365
10.3.1.1/10-365
Sections
Affected
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 10-1. Revision History
- Update flow-chart of interrupt routine for 10-bit address
- Revise Table1-5
- Backward compatible for IBAD bit name
Description of Changes
361