sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 458

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Serial Communication Interface (S12SCIV5)
12.5.3.1.6
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the
RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.
12.5.3.1.7
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single
wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative
status register 1. This flag is also cleared if the bit error detect feature is disabled.
12.5.3.1.8
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the
SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
12.5.4
The SCI interrupt request can be used to bring the CPU out of wait mode.
12.5.5
An active edge on the receive input can be used to bring the CPU out of stop mode.
458
Recovery from Wait Mode
Recovery from Stop Mode
RXEDGIF Description
BERRIF Description
BKDIF Description
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor