sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 115

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
1
2.3.71
2.3.72
Freescale Semiconductor
Address 0x028E
Address 0x028F
PIF1AD
In order to enable the Key Wakeup function, need to set the ATDIENL first.
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Read: Anytime.
Field
Field
PIER
Reset
Reset
7-0
3-0
W
W
R
R
Port AD interrupt flag—
Each flag is set by an active edge on the associated input pin. To clear this flag, write logic level 1 to the
corresponding bit in the PIF1AD register. Writing a 0 has no effect.
1 Active falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
Port R interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port R.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Port R Interrupt Enable Register (PIER)
Port R Interrupt Flag Register (PIFR)
0
0
0
0
7
7
0
0
0
0
6
6
Figure 2-69. Port R Interrupt Enable Register (PIER)
Figure 2-70. Port R Interrupt Flag Register (PIFR)
Table 2-59. PIF1AD Register Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-60. PIER Register Field Descriptions
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PIER3
PIFR3
3
0
3
0
1
PIER2
PIFR2
Port Integration Module (S12HYPIMV1)
0
0
2
2
Access: User read/write
Access: User read/write
PIER1
PIFR1
0
0
1
1
PIER0
PIFR0
0
0
0
0
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1
1