sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 563

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Chapter 16
48 KByte Flash Module (S12FTMRC48K1V1)
16.1
The FTMRC48K1 module implements the following:
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents. The user interface to the
memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is
written to with the command, global address, data, and any required command parameters. The memory
controller must complete the execution of a command before the FCCOB register can be written to with a
new command.
The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus
cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased
bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on D-Flash memory. It
is not possible to read from D-Flash memory while a command is executing on P-Flash memory.
Simultaneous P-Flash and D-Flash operations are discussed in
Freescale Semiconductor
Revision
Number
V01.12
V01.13
•
•
48 Kbytes of P-Flash (Program Flash) memory
4 Kbytes of D-Flash (Data Flash) memory
Introduction
25 May 2009
25 Sep 2009
Revision
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
Date
16.3.2.1/16-572
16.4.3.2/16-589
16.3.2/16-570
16.6/16-611
Sections
Affected
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 16-1. Revision History
- Initial version
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
CAUTION
Description of Changes
Section
16.4.4.
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