sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 452

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Serial Communication Interface (S12SCIV5)
12.4.6.5
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated
bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside
the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical
values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the
RT8, RT9, and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge
within the frame. Re synchronization within frames will correct a misalignment between transmitter bit
times and receiver bit times.
12.4.6.5.1
Figure 12-28
a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is:
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
452
((151 – 144) / 151) x 100 = 4.63%
((167 – 160) / 167) X 100 = 4.19%
Baud Rate Tolerance
shows how much a slow received frame can be misaligned without causing a noise error or
Slow Data Tolerance
RT Clock
Receiver
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
MSB
Figure
Figure
Figure 12-28. Slow Data
12-28, the receiver counts 151 RTr cycles at the point when
12-28, the receiver counts 167 RTr cycles at the point when
Samples
Data
Stop
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