sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 188

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

S12S Debug Module (S12SDBGV2)
6.3.2.2
188
Address: 0x0021
DBGBRK
COMRV
Reset
Field
TRIG
ARM
BDM
POR
1–0
7
6
4
3
W
R
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user
software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state
sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK
and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the
DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger
alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect.
In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session.
The session is ended by setting TRIG and ARM simultaneously.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background
Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the
ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
0 No Breakpoint generated
1 Breakpoint generated
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
TBF
Debug Status Register (DBGSR)
—
0
7
on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion
of the tracing session. If tracing is not enabled, the breakpoint is generated immediately.
COMRV
00
01
10
11
= Unimplemented or Reserved
0
0
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 6-4. Debug Status Register (DBGSR)
Visible Comparator
Table 6-3. DBGC1 Field Descriptions
Comparator A
Comparator B
Comparator C
0
0
0
5
Table 6-4. COMRV Encoding
None
0
0
0
4
Description
Visible Register at 0x0027
0
0
0
3
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
6-4.
0
0
2
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0