sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 294

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog-to-Digital Converter (ADC12B8CV1) Block Description
8.3.2.6
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Read: Anytime
Write: Anytime
294
Module Base + 0x0005
Reset
SCAN
Field
SC
6
5
W
R
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5.
0 Special channel conversions disabled
1 Special channel conversions enabled
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means
external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
ATD Control Register 5 (ATDCTL5)
0
0
7
= Unimplemented or Reserved
SMP2
SC
0
6
1
Figure 8-8. ATD Control Register 5 (ATDCTL5)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 8-14. ATDCTL5 Field Descriptions
SMP1
SCAN
Table 8-13. Sample Time Select
Table 8-15
1
0
5
SMP0
lists the coding.
MULT
1
0
4
Description
ATD Clock Cycles
CD
0
3
Sample Time
in Number of
24
CC
0
2
Freescale Semiconductor
CB
0
1
CA
0
0

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