sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 87

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
2.3.24
Freescale Semiconductor
Address 0x024A
Read: Anytime.
Write: Anytime.
DDRS
DDRS
DDRS
DDRS
Field
Reset
7
6
5
4
W
R
Port S data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, the IIC determines the pin direction, it will force as open-drain output
Else if PWM3 is routing to PS and PWM3 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM2 is routing to PS and PWM2 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM1 is routing to PS and PWM1 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, it will force as open-drain output
Else if PWM0 is routing to PS and PWM0 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRS7
Port S Data Direction Register (DDRS)
0
7
DDRS6
0
6
Figure 2-22. Port S Data Direction Register (DDRS)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-21. DDRS Register Field Descriptions
DDRS5
0
5
DDRS4
0
4
Description
DDRS3
3
0
DDRS2
Port Integration Module (S12HYPIMV1)
0
2
DDRS1
Access: User read/write
0
1
DDRS0
0
0
87
1