sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 81

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

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2.3.16
2.3.17
Freescale Semiconductor
Address 0x0242
Address 0x0243
Read: Anytime
Write: Anytime
DDRT
DDRT
Field
Reset
Reset
7-4
3-0
W
W
R
R
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM0 output compare channel is enabled, it will be forced as output.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding TIM1 output compare channel is enabled, it will be forced as output.
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRT7
RDRT7
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
DDRT6
RDRT6
0
0
6
6
Figure 2-15. Port T Reduced Drive Register (RDRT)
Figure 2-14. Port T Data Direction Register (DDRT)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-14. DDRT Register Field Descriptions
DDRT5
RDRT5
0
0
5
5
DDRT4
RDRT4
NOTE
0
0
4
4
Description
DDRT3
RDRT3
3
0
3
0
RDRT2
DDRT2
Port Integration Module (S12HYPIMV1)
0
0
2
2
DDRT1
RDRT1
Access: User read/write
Access: User read/write
0
0
1
1
DDRT0
RDRT0
0
0
0
0
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