sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 330

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1. Read: Anytime
Module Base + 0x0018 to Module Base + 0x001B
1. Read: Anytime
Module Base + 0x0010 to Module Base + 0x0013
Freescale’s Scalable Controller Area Network (S12MSCANV3)
9.3.2.17
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
330
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AC[7:0]
Field
7-0
Figure 9-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Reset
Figure 9-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
W
R
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
MSCAN Identifier Acceptance Registers (CANIDAR0-7)
AC7
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 9-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
AC6
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
0
6
AC5
AC5
0
5
5
0
AC4
AC4
0
4
Description
0
4
AC3
AC3
0
3
3
0
AC2
AC2
0
2
0
2
Access: User read/write
Freescale Semiconductor
Access: User read/write
Section 9.3.3.1,
AC1
Section 9.4.3,
AC1
0
1
1
0
AC0
AC0
0
0
0
0
(1)
(1)