sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 376

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Inter-Integrated Circuit (IICV3) Block Description
10.3.1.6
This register contains the variables used in general call and in ten-bit address.
Read and write anytime
10.4
This section provides a complete functional description of the IICV3.
10.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure
376
RESERVED
ADR[10:8]
ADTYPE
Reset
GCEN
Field
5,4,3
2:0
7
6
W
R
10-10.
Module Base + 0x0005
Functional Description
GCEN
General Call Enable.
0 General call is disabled. The module dont receive any general call data and address.
1 enable general call. It indicates that the module can receive address and any data.
Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters
slave mode.
0 7-bit address
1 10-bit address
Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0.
Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted
(ADTYPE = 1).
I-Bus Protocol
IIC Control Register 2(IBCR2)
0
7
ADTYPE
0
6
Figure 10-9. IIC Bus Control Register 2(IBCR2)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 10-10. IBCR2 Field Descriptions
0
0
5
0
0
4
Description
0
0
3
ADR10
0
2
Freescale Semiconductor
ADR9
0
1
ADR8
0
0