sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 161

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

5.1.2.3
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3
A block diagram of the BDM is shown in
Freescale Semiconductor
System
Host
Block Diagram
Low-Power Modes
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
UNSEC
TRACE
SDV
Interface
Serial
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Control
Data
Figure 5-1. BDM Block Diagram
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
5-1.
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
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