sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 125

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

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2.3.84
Freescale Semiconductor
Address 0x029B
Read: Always reads 0x00
Write: Unimplemented
DDRV
DDRV
Field
Reset
1
0
W
R
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM5 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channel is enabled, it will be forced as output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be open drain output, also the input buffer
is enabled
Else if PWM4 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
PIM Reserved Registers
0
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTV or PTIV registers, when changing the
DDRV register.
= Unimplemented or Reserved
Table 2-70. DDRV Register Field Descriptions (continued)
0
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 2-82. PIM Reserved Registers
0
0
5
NOTE
0
0
4
Description
u = Unaffected by reset
3
0
0
Port Integration Module (S12HYPIMV1)
0
0
2
0
0
1
Access: User read
0
0
0
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