sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 93

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
1
2.3.34
Freescale Semiconductor
Address 0x025B
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
DDRP
DDRP
RDRP
Field
Field
Reset
6-0
7-0
7
W
R
Port P data direction—
This register controls the data direction of pin 7.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this
pin is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel.
In this case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
RDRP7
Port P Reduced Drive Register (RDRP)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
RDRP6
0
6
Figure 2-32. Port P Reduced Drive Register (RDRP)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-29. DDRP Register Field Descriptions
Table 2-30. RDRP Register Field Descriptions
RDRP5
0
5
RDRP4
NOTE
0
4
Description
Description
RDRP3
3
0
RDRP2
Port Integration Module (S12HYPIMV1)
0
2
RDRP1
Access: User read/write
0
1
RDRP0
0
0
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