LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 80

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

3.1.6 SCSI Bus Interface Signals
Table 3.7
3-10
Name
SCLK
SD[15:0]/,
SDP[1:0]/
SCTRL/
SDIR[15:0]
SDIRP[1:0]
(SDIPR1 not
available on
LSI53C825AJ)
SELDIR
SCSI Bus Interface Signals
113, 115, 116,
103, 105, 106,
107, 108, 110,
92, 90, 95, 91,
131, 132, 134,
121, 122, 124,
125, 126, 127,
111, 112, 101
117, 85, 86,
87, 89, 102,
97, 98, 100,
135, 80, 81,
82, 83, 120,
130, 119
Pin No.
96, 94
Table 3.7
Signal Descriptions
129
56
76
describes the SCSI Bus Interface Signals group:
Type Description
I/O
I/O
O
O
O
I
SCLK is used to derive all SCSI-related timings. The speed
of this clock is determined by the application’s requirements;
in some applications SCLK may be sourced internally from
the PCI bus clock (CLK). If SCLK is internally sourced, then
the SCLK pin should be tied LOW.
SCSI Data includes the following data lines and parity
signals: SD[15:0]/ (16-bit SCSI data bus), and SDP[1:0]/
(SCSI data parity bits).
SCSI Control includes the following signals:
SC_D/
SI_O/
SMSG/
SREQ/
SACK/
SBSY/
SATN/
SRST/
SSEL/
Driver direction control for SCSI data lines.
Driver direction control for SCSI parity signals. In the
LSI53C825AJ, this pin is replaced by the TCK JTAG signal. If
the device is used in a wide differential system, use the
SDIRP0 pin to control the direction of the differential
transceiver for both the SP0 and SP1 signals. The SDIRP0
signal is capable of driving both direction inputs from a
transceiver.
Driver Enable Control for SCSI SEL/ signal.
SCSI phase line, command/data
SCSI phase line, input/output
SCSI phase line, message
Data handshake signal from target device
Data handshake signal from initiator device
SCSI bus arbitration signal, busy
SCSI Attention, the initiator is requesting a
message out phase
SCSI bus reset
SCSI bus arbitration signal, select device