LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 160

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-72
M/A
CMP
SEL
RSL
SGE
Registers
SCSI Phase Mismatch - Initiator Mode; SCSI
ATN Condition - Target Mode
In the initiator mode, this bit is set when the SCSI phase
asserted by the target and sampled during SREQ/ does
not match the expected phase in the
Latch (SOCL)
automatically written by SCSI SCRIPTS. In the target
mode, this bit is set when the initiator asserts SATN/. See
the Disable Halt on Parity Error or SATN/ Condition bit in
the
information on when this status is actually raised.
Function Complete
Indicates full arbitration and selection sequence is
completed.
Selected
Indicates the LSI53C825A is selected by a SCSI initiator
device. Set the Enable Response to Selection bit in the
SCSI Chip ID (SCID)
Reselected
Indicates the LSI53C825A is reselected by a SCSI target
device. Set the Enable Response to Reselection bit in the
SCSI Chip ID (SCID)
SCSI Gross Error
The following conditions are considered SCSI Gross
Errors:
Data underflow – reading the SCSI FIFO when no
data is present.
Data overflow – writing to the SCSI FIFO while it is
full.
Offset underflow – receiving a SACK/ pulse in the
target mode before the corresponding SREQ/ is sent.
Offset overflow – receiving a SREQ/ pulse in the
initiator mode, and exceeding the maximum offset
(defined by the MO[3:0] bits in the
(SXFER)
A phase change in the initiator mode, with an
outstanding SREQ/SACK offset.
SCSI Control One (SCNTL1)
register).
register. This expected phase is
register for this to occur.
register for this to occur.
register for more
SCSI Output Control
SCSI Transfer
7
6
5
4
3