LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 194

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5-10
SCSI SCRIPTS Instruction Set
4. The LSI53C825A transfers the number of bytes
5. If the SATN/ signal is asserted by the Initiator or a
– If the SCSI Group Code is either Group 0, Group 1,
– If the Vendor Unique Enhancement 1 (VUE1) bit
– If the Vendor Unique Enhancement 1 bit is clear
– If any other Group Code is received, the
specified in the
starting at the address specified in the
Address (DNAD)
a data transfer ends on an odd byte boundary, the
LSI53C825A stores the last byte in the
Residue (SWIDE)
This byte is combined with the first byte from the
subsequent transfer so that a wide transfer can be
completed.
parity error occurred during the transfer, the transfer
can optionally be halted and an interrupt generated.
The Disable Halt on Parity Error or ATN bit in the
SCSI Control One (SCNTL1)
whether the LSI53C825A halts on these conditions
immediately, or waits until completion of the current
Move.
Group 2, or Group 5, and if the Vendor Unique
Enhancement 1 (VUE1) bit
(SCNTL2), bit 1) is clear, then the LSI53C825A
overwrites the
with the length of the Command Descriptor Block:
6, 10, or 12 bytes.
(SCSI Control Two
LSI53C825A receives the number of bytes in the
byte count regardless of the group code.
and group code is vendor unique, the LSI53C825A
receives the number of bytes in the count.
Counter (DBC)
LSI53C825A requests the number of bytes
specified in the
If the
0x000000, an illegal instruction interrupt is
generated.
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
register. If the Opcode bit is set and
register is not modified and the
DMA Byte Counter (DBC)
register during a receive operation.
(SCNTL2), bit 1) is set, the
register controls
(SCSI Control Two
register contains
DMA Next
SCSI Wide
DMA Byte
register
register
register.