LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 117

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

EWS
CCF[2:0]
Operating Registers
Note:
For additional information on how the synchronous transfer
rate is determine, refer to
tion.”
Table 4.3
Enable Wide SCSI
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are done
16 bits at a time, with the least significant byte on
SD[7:0]/ and SDP0/ and the most significant byte on
SD[15:8]/, SDP1/. Command, Status, and Message
phases are not affected by this bit.
Clearing this bit also clears the Wide SCSI Receive bit in
the
the presence of a valid data byte in the
idue (SWIDE)
Clock Conversion Factor
These bits select a factor by which the frequency of
SCLK is divided before being presented to the SCSI core.
The synchronous portion of the SCSI core can be run at
a different clock rate for Fast SCSI, using the
Synchronous Clock Conversion Factor bits. The bit
encoding is displayed in
are reserved.
CCF2
SCF2
SCSI Control Two (SCNTL2)
0
0
0
0
1
1
1
1
SCF1
CCF1
0
0
1
1
0
0
1
1
Synchronous Clock Conversion Factor
register.
CCF0
SCF0
0
1
0
1
0
1
0
1
Table
Chapter 2, “Functional Descrip-
Frequency
Reserved
Reserved
Reserved
SCLK/1.5
SCLK/3
SCLK/1
SCLK/2
SCLK/3
Factor
4.3. All other combinations
register, which indicates
SCSI Clock (MHz)
SCSI Wide Res-
50.01–75.0
16.67–25.0
25.01–37.5
37.51–50.0
50.01–75.0
–
–
–
[2:0]
4-29
3