LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 145

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x21 (0xA1)
Chip Test Four (CTEST4)
Read/Write
BDIS
Operating Registers
BDIS
7
0
Note:
ZMOD
6
0
If trying to calculate the total number of bytes in both the
DMA FIFO and SCSI logic, see
Paths,”
difference between these two counters represents the
number of bytes remaining in the DMA FIFO.
The following steps determine how many bytes are left in
the DMA FIFO when an error occurs, regardless of the
transfer direction:
Step 1. If the DMA FIFO size is set to 88 bytes, subtract
If the DMA FIFO size is set to 536 bytes (using bit 5 of
the
10 least significant bits of the
register from the 10-bit value of the DMA FIFO Byte
offset Counter, which consists of bits [1:0] in the
Test Five (CTEST5)
FIFO (DFIFO)
Step 2. If the DMA FIFO size is set to 88 bytes, AND the
Burst Disable
When set, this bit causes the LSI53C825A to perform
back to back cycles for all transfers. When this bit is
cleared, back to back transfers for opcode fetches and
burst transfers for data moves are performed.
Chip Test Five (CTEST5)
ZSD
in
5
0
Chapter 2, “Functional Description.”
the seven least significant bits of the
Counter (DBC)
the
result with 0x7F for a byte count between zero
and 64. If the DMA FIFO size is set to 536 bytes,
AND the result with 0x3FF for a byte count
between zero and 536.
DMA FIFO (DFIFO)
SRTM
register.
4
0
register and bits [7:0] of the
MPEE
register from the 7-bit value of
3
0
register), subtract the
DMA Byte Counter (DBC)
Section 2.4.8.1, “Data
register.
2
0
FBL[2:0]
0
DMA Byte
Chip
DMA
0
0
4-57
7