LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 136

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-48
31
0
0
0
0
0
0
0
Registers: 0x10–0x13 (0x90–0x93)
Data Structure Address (DSA)
Read/Write
DSA
Register: 0x14 (0x94)
Interrupt Status (ISTAT)
Read/Write
This is the only register that is accessible by the host CPU while a
LSI53C825A is executing SCRIPTS (without interfering in the operation
of the function). It is used to poll for interrupts if hardware interrupts are
disabled. Read this register after servicing an interrupt to check for
stacked interrupts. For more information on interrupt handling refer to
Chapter 2, “Functional Description.”
ABRT
Registers
0
ABRT
0
7
0
0
0
SRST
0
6
0
Data Structure Address
This 32-bit register contains the base address used for all
table indirect calculations. The
(DSA)
but it is possible for a SCRIPTS Memory Move to load the
DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register is preserved. The power-up value
of this register is indeterminate.
Abort Operation
Setting this bit aborts the current operation under
execution by the LSI53C825A. If this bit is set and an
interrupt is received, clear this bit before reading the
Status (DSTAT)
interrupts from being generated. The sequence to abort
any operation is:
1. Set this bit.
0
0
SIGP
0
DSA[31:0]
5
0
register is usually loaded prior to starting an I/O,
0
0
SEM
0
4
0
register to prevent further aborted
0
0
0
CON
3
0
0
0
Data Structure Address
0
INTF
2
0
0
0
0
SIP
1
0
0
0
0
DIP
[31:0]
DMA
0
0
0
0
0
7