LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 164

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-76
UDC
RST
PAR
Registers
Unexpected Disconnect
This bit is set when the LSI53C825A is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid
when the LSI53C825A operates in the initiator mode.
When the SCSI function operates in the low level mode,
any disconnect causes an interrupt, even a valid SCSI
disconnect. This bit is also set if a selection time-out
occurs (it may occur before, at the same time, or stacked
after the STO interrupt, since this is not considered an
expected disconnect).
SCSI RST/ Received
This bit is set when the LSI53C825A detects an active
SRST/ signal, whether the reset is generated external to
the chip or caused by the Assert SRST/ bit in the
Control One (SCNTL1)
detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SRST/ signal.
Parity Error
This bit is set when the LSI53C825A detects a parity
error while receiving SCSI data. The Enable Parity
Checking bit (bit 3 in the
Data Overflow – writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting
the SCSI FIFO.
Offset Underflow – the LSI53C825A is operating in
the target mode and a SACK/ pulse is received when
the outstanding offset is zero.
Offset Overflow – the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the
maximum synchronous offset defined by the
Transfer (SXFER)
A phase change occurs with an outstanding
synchronous offset when the LSI53C825A is
operating as an initiator.
Residual data in the synchronous data FIFO – a
transfer other than synchronous data receive is
started with data left in the synchronous data FIFO.
register.
register. This SCSI reset
SCSI Control Zero (SCNTL0)
SCSI
SCSI
2
1
0