LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 44

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.6 Loopback Mode
2-20
Big/little endian mode selection has the most effect on individual byte
access. Internally, the LSI53C825A adjusts the byte control logic of the
DMA FIFO and register decodes to enable the appropriate byte lane. The
registers always appear on the same byte lane, but the address of the
register are repositioned.
Data to be transferred between system memory and the SCSI bus
always starts at address zero and continues through address ‘n’ – there
is no byte ordering in the chip. The first byte in from the SCSI bus goes
to address 0, the second to address 1, etc. Going out onto the SCSI bus,
address zero is the first byte out on the SCSI bus, address 1 is the
second byte, etc. The only difference is that in a little endian system,
address 0 is on byte lane 0, and in big endian mode address zero is on
byte lane 3.
Correct SCRIPTS are generated if the SCRIPTS compiler is run on a
system that has the same byte ordering as the target system. Any
SCRIPTS patching in memory must patch the instruction with the byte
ordering that the SCRIPTS processor expects.
Software drivers for the LSI53C825A should access registers by their
logical name (i.e., SCNTL0) rather than by their address. The logical
name should be equated to the register’s big endian address in big
endian mode (SCNTL0 = 0x03), and its little endian address in little
endian mode (SCNTL0 = 0x00). This way, there is no change to the
software when moving from one mode to the other; only the equate
statement setting the operating modes needs to be changed.
Addressing of registers from within a SCRIPTS instruction is independent
of bus mode. Internally, the LSI53C825A always operates in little endian
mode.
The LSI53C825A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the
register, the LSI53C825A allows control of all SCSI signals, whether the
LSI53C825A is operating in initiator or target mode. For more information
on this mode of operation, refer to the SCSI SCRIPTS Processors
Programming Guide .
Functional Description
Chip Test One (CTEST1)