LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 159

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

31
x
x
x
x
x
x
x
COM
Registers: 0x3C–0x3F (0xBC–0xBF)
Adder Sum Output (ADDER)
Read Only
ADDER
Register: 0x40 (0xC0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
(SIST0)
bit. For more information on interrupts see
Description.”
Operating Registers
x
M/A
x
7
0
x
register. An interrupt is masked by clearing the appropriate mask
x
CMP
x
6
0
LSI53C700 Family Compatibility
When the COM bit is cleared, the LSI53C825A behaves
in a manner compatible with the LSI53C700 family;
selection/reselection IDs are stored in both the
Selector ID (SSID)
registers.
When this bit is set, the ID is stored only in the
Destination ID (SDID)
being overwritten if a selection/reselection occurs during
a DMA register-to-register operation. This bit is not
affected by a software reset.
Adder Sum Output
This register contains the output of the internal adder,
and is used primarily for test purposes. The power-up
value for this register is indeterminate.
x
x
SEL
x
5
0
ADDER
x
x
RSL
x
4
0
x
and
x
register, protecting the SFBR from
SCSI First Byte Received (SFBR)
x
SGE
SCSI Interrupt Status Zero
3
0
x
Chapter 2, “Functional
x
x
UDC
2
0
x
x
x
RST
1
0
x
x
SCSI
SCSI
x
PAR
[31:0]
0
0
x
4-71
0
x
0