LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 70

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.5 Power Management
2.5.1 Power State D0
2.5.2 Power State D3
2-46
This feature complies with the PCI Bus Power Management Interface
Specification, Revision 1.0. The PCI Function Power States are defined
in that specification: D0, D1, D2, and D3. D0 and D3 are required by
specification, and D1 and D2 are optional. D0 is the maximum powered
state, and D3 is the minimum powered state. Power state D3 is further
categorized as D3hot or D3cold. A function that is powered off is said to
be in the D3cold power state.
The power states for the SCSI function are independently controlled
through two power state bits that are located in the PCI Configuration
Space register 0x44. The bits are encoded as:
Power states D1 and D2 are not discussed because they have not been
implemented as a new feature.
The Power states – D0 and D3 – are described below in conjunction with
each SCSI function. Power state actions are separate for each function.
Power state D0 is the maximum power state and is the power-up default
state for each function.
Power state D3 is the minimum power state, which includes subsettings
called D3hot and D3cold. The devices are considered to be in power
state D3cold when power is removed from them. D3cold can transition
to D0 by applying Vcc and resetting the device. D3hot allows the device
to transition to D0 using software. To obtain power reduction in D3hot,
the SCSI clock and the SCSI clock doubler Phase Lock Loop (PLL) are
disabled. Furthermore, the function’s soft reset is continually asserted
while in power state D3, which clears all pending interrupts and 3-states
the SCSI bus. In addition, the function’s PCI
cleared.
Functional Description
00b
01b
10b
11b
D0
Reserved
Reserved
D3
Command
register is