LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 224

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5.8 Load and Store Instructions
5-40
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The Load and Store instructions are represented by two Dword opcodes.
The first Dword contains the
Counter (DBC)
SCRIPTS Pointer Save (DSPS)
location of where to Load and Store, or the offset from the
Address
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
The SIOM and DIOM bits in the
whether the destination or source address of the instruction is in Memory
space or I/O space, as illustrated in the following table. The Load and
Store utilizes the PCI commands for I/O read and I/O write to access the
I/O space.
SCSI SCRIPTS Instruction Set
Bit A1
Bit
SIOM (Load)
DIOM (Store)
0
0
1
1
(DSA), depending on the value of bit 28 (DSA Relative).
Bit A0
0
1
0
1
register values. The second Dword contains the
Number of Bytes Allowed to Load and Store
One, two, three or four
One, two, or three
One or two
One
Source
Memory
Register
DMA Command (DCMD)
DMA Mode (DMODE)
value. This is either the actual memory
Destination
Register
Memory
register determine
and
Data Structure
DMA Byte
DMA