LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 31

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

When these conditions are met, the LSI53C825A issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Write and Invalidate command
can write multiple cache lines of data in a single bus ownership. The chip
issues a burst transfer as soon as it reaches a cache line boundary. The
size of the transfer is not automatically the cache line size, but rather a
multiple of the cache line size specified in the Revision 2.1 of the PCI
specification. The logic selects the largest multiple of the cache line size
based on the amount of data to transfer, with the maximum allowable
burst size being that determined from the
size bits and
transfers are not desired, the
the cache line size and the chip only issues single cache line transfers.
After each data transfer, the chip reevaluates the burst size based on the
amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the DMODE burst
size. The most likely scenario of this scheme is that the chip selects the
DMODE burst size after alignment, and issue bursts of this size. The
burst size is, in effect, throttled down toward the end of a long Memory
Move or Block Move transfer until only the cache line size burst size is
left. The chip finishes the transfer with this burst size.
Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out occurs, the LSI53C825A continues to transfer up until a
cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines it continues to transfer until the
next cache boundary is reached.
PCI Addressing
The
(2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to
the
The chip has enough bytes in the
at least one full cache line burst.
The chip is aligned to a cache line boundary.
DMA Mode (DMODE)
Cache Line Size
Chip Test Five
register contains a legal burst size in Dwords
(CTEST5), bit 2. If multiple cache line size
DMA Mode (DMODE)
burst size.
DMA FIFO (DFIFO)
DMA Mode (DMODE)
burst size to exactly
to complete
burst
2-7