LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 64

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LSI53C825AJ

Manufacturer Part Number
LSI53C825AJ
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53C825AJ

Lead Free Status / RoHS Status
Not Compliant
2.4.13.6 Halting in an Orderly Fashion
2-40
SIST1 instead of being stacked behind another interrupt. When another
condition occurs that generates an interrupt, the bit corresponding to the
earlier masked nonfatal interrupt is still set.
A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).
As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon
as the DMA FIFO is empty.
When an interrupt occurs, the LSI53C825A attempts to halt in an orderly
fashion.
Functional Description
If the interrupt occurs in the middle of an instruction fetch, the fetch
is completed, except in the case of a Bus Fault. Execution does not
begin, but the DSP points to the next instruction since it is updated
when the current instruction is fetched.
If the DMA direction is a write to memory and a SCSI interrupt
occurs, the LSI53C825A attempts to flush the
memory before halting. Under any other circumstances only the
current cycle is completed before halting, so the DFE bit in
Status (DSTAT)
DMA FIFO.
SCSI SREQ/SACK handshakes that have begun are completed
before halting.
The LSI53C825A attempts to clean up any outstanding synchronous
offset before halting.
In the case of Transfer Control Instructions, once instruction
execution begins it continues to completion before halting.
should be checked to see if any data remains in the
DMA FIFO (DFIFO)
DMA
to

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