LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 61

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.13.3 Fatal vs. Nonfatal Interrupts
bit is clear, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO)
bits before continuing. The CLF bit is bit 2 in
The CSF bit is bit 1 in
DSTAT – The
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit. It does not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the
be checked after any DMA interrupt. If the DFE bit is cleared, then the
FIFOs must be cleared by setting the CLF (Clear DMA FIFO) and CSF
(Clear SCSI FIFO) bits, or flushed by setting the FLF (Flush DMA FIFO)
bit.
SIEN0 and SIEN1 – The
Interrupt Enable One (SIEN1)
for the SCSI interrupts in
Interrupt Status One
DIEN – The
register for DMA interrupts in
DCNTL – When bit 1 in this register is set, the IRQ/ pin is not asserted
when an interrupt condition occurs. The interrupt is not lost or ignored,
but merely masked at the pin. Clearing this bit when an interrupt is
pending immediately causes the IRQ/ pin to assert. As with any register
other than
except by a SCRIPTS instruction during SCRIPTS execution.
A fatal interrupt, as the name implies, always causes SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking will be
discussed in
by the DIP bit in
Status (DSTAT)
PCI Cache Mode
Interrupt Status
DMA Interrupt Enable (DIEN)
Section 2.4.13.4, “Masking.”
DMA Status (DSTAT)
being set) are fatal.
Interrupt Status (ISTAT)
(SIST1).
Chip Test Three
SCSI Interrupt Enable Zero (SIEN0)
SCSI Interrupt Status Zero (SIST0)
(ISTAT), this register cannot be accessed
registers are the interrupt enable registers
DMA Status
DMA Status (DSTAT)
register contains the DMA-type
(CTEST3).
and one or more bits in
All DMA interrupts (indicated
register is the interrupt enable
(DSTAT).
Chip Test Three
register should
(CTEST3).
and
and
DMA
SCSI
SCSI
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