LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 196

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5-12
SCSIP[2:0]
TC[23:0]
SCSI SCRIPTS Instruction Set
5. If the SCSI phase bits do not match the value stored
6. During a Message-Out phase, after the LSI53C825A
7. When the LSI53C825A is performing a block move for
SCSI Phase
This 3-bit field defines the SCSI information transfer
phase. When the LSI53C825A operates in Initiator mode,
these bits are compared with the latched SCSI phase bits
in the
LSI53C825A operates in Target mode, it asserts the
phase defined in this field. The following table describes
the possible combinations and the corresponding SCSI
phase.
MSG C_D
0
0
0
0
1
1
1
1
Transfer Counter
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C825A and system memory.
The field is stored in the
register. When the LSI53C825A transfers data to/from
memory, the
in the
LSI53C825A generates a phase mismatch interrupt
and the instruction is not executed.
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C825A deasserts SATN/ during the final
SREQ/SACK/ handshake.
Message-In phase, it does not deassert the SACK/
signal for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
0
0
1
1
0
0
1
1
SCSI Status One (SSTAT1)
SCSI Status One (SSTAT1)
I_O
0
1
0
1
0
1
0
1
DMA Byte Counter (DBC)
SCSI Phase
Data-Out
Data-In
Command
Status
Reserved-Out
Reserved-In
Message-Out
Message-In
DMA Byte Counter (DBC)
register. When the
register, the
register is
[26:24]
[23:0]