LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 49

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Step 2. Read bit 5 in the
Step 3. Read bit 6 in the
Asynchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 88 bytes, look at the
PCI Cache Mode
Counter (DBC)
(DFIFO)
between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
Test Five (CTEST5)
bits of the
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.
Two (SSTAT2)
SCSI Output Data Latch (SODL)
SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte in the
is full, respectively. Checking this bit also reveals bytes left in
the
Move operation with an odd byte count.
Two (SSTAT2)
SODR register. If bit 6 is set in the
or
the most significant byte in the SODR register is full,
respectively.
(DFIFO)
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the
Counter (DBC)
(DFIFO)
between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the
Test Five (CTEST5)
bits of the
value of the DMA FIFO Byte Offset Counter, which consists of
SCSI Status Two
SCSI Output Data Latch (SODL)
and
register. AND the result with 0x7F for a byte count
register. AND the result with 0x7F for a byte count
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
DMA Byte Counter (DBC)
registers to determine if any bytes are left in the
registers to determine if any bytes are left in the
Chip Test Five (CTEST5)
register from the 7-bit value of the
register from the 7-bit value of the
SCSI Status Zero (SSTAT0)
SCSI Status Zero (SSTAT0)
(SSTAT2), then the least significant byte or
register), subtract the 10 least significant
register), subtract the 10 least significant
SCSI Output Data Latch (SODL)
register. If bit 5 is set in the
SCSI Status Zero (SSTAT0)
register from the 10-bit
register from a Chained
register from the 10-bit
registers and calculate
register and bits [7:0]
and
and
DMA Byte
SCSI Status
SCSI Status
DMA FIFO
DMA FIFO
DMA FIFO
register
Chip
Chip
2-25