LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 119

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x05 (0x85)
SCSI Transfer (SXFER)
Read/Write
TP[2:0]
Operating Registers
7
0
Note:
TP[2:0]
0
When using Table Indirect I/O commands, bits [7:0] of this
register are loaded from the I/O data structure.
For additional information on how the synchronous transfer
rate is determined, refer to
tion.”
SCSI Synchronous Transfer Period
These bits determine the SCSI synchronous transfer
period used by the LSI53C825A when sending
synchronous SCSI data in either the initiator or target
mode. These bits control the programmable dividers in
the chip.
The synchronous transfer period the LSI53C825A should
use when transferring SCSI data is determined in the
following example:
7
6
TP2
5
0
0
0
0
0
1
1
1
1
5
Highest
4
3
4
0
2
TP1
0
0
1
1
0
0
1
1
1
0
Chapter 2, “Functional Descrip-
0
15 14 13 12 11 10
MO[4:0]
TP0
0
0
1
0
1
0
1
0
1
Lowest
0
XFERP
10
11
4
5
6
7
8
9
9
0
0
[7:5]
4-31
8