LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 142

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-54
TEOP
DREQ
DACK
Register: 0x1B (0x9B)
Chip Test Three (CTEST3)
Read/Write
V[3:0]
FLF
Registers
7
x
Note:
x
Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.
bit is clear, the
Scratch Register B (SCRATCHB)
normal operation.
SCSI True End of Process
This bit indicates the status of the LSI53C825A internal
TEOP signal. The TEOP signal acknowledges the
completion of a transfer through the SCSI portion of the
LSI53C825A. When this bit is set, TEOP is active. When
this bit is cleared, TEOP is inactive.
Data Request Status
This bit indicates the status of the LSI53C825A internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is cleared, DREQ is inactive.
Data Acknowledge Status
This bit indicates the status of the LSI53C825A internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is cleared, DACK/ is
active.
Chip Revision Level
These bits identify the chip revision level for software
purposes. It should have the same value as the lower
nibble of the PCI
the configuration space.
Flush DMA FIFO
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the
V[3:0]
x
Scratch Register A (SCRATCHA)
4
x
Revision ID
FLF
3
0
register, at address 0x08 in
CLF
2
0
registers return to
FM
1
0
and
WRIE
DMA
0
0
[7:4]
2
1
0
3