LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 76

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

3.1 PCI Bus Interface Signals
3.1.1 System Signals
Table 3.2
3-6
Name Pin No. Type Description
CLK
RST/
145
144
System Signals
I
I
The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups:
Data
Reporting
Signals,
Table 3.2
Signal Descriptions
Clock provides timing for all transactions on the PCI bus and is an input to
every PCI device. All other PCI signals are sampled on the rising edge of
CLK, and other timing parameters are defined with respect to this edge. This
clock can optionally be used as the SCSI core clock; however, the
LSI53C825A is not able to achieve Fast SCSI transfer rates.
Reset forces the PCI sequencer of each device to a known state. All t/s and
s/t/s signals are forced to a high impedance state, and all internal logic is
reset. The RST/ input is synchronized internally to the rising edge of CLK.
The CLK input must be active while RST/ is active to properly reset the
device.
Signals,
External Memory Interface
describes the signals for the System Signals group:
Signals,
Interface Control
SCSI Bus Interface
Signals,
Signals, and
System
Signals,
Arbitration
Signals,
Additional Interface
JTAG Signals.
Signals,
Address and
Error