LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 156

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-68
Register: 0x39 (0xB9)
DMA Interrupt Enable (DIEN)
Read/Write
R
MDPE
BF
ABRT
SSI
SIR
R
IID
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
interrupt is masked by clearing the appropriate mask bit. Masking an
interrupt prevents IRQ from being asserted for the corresponding
interrupt, but the status bit is still set in the
Masking an interrupt does not prevent setting the
DIP. All DMA interrupts are considered fatal, therefore SCRIPTS stops
running when this condition occurs, whether or not the interrupt is
masked. Setting a mask bit enables the assertion of IRQ for the
corresponding interrupt. (A masked nonfatal interrupt does not prevent
unmasked or fatal interrupts from getting through; interrupt stacking
begins when either the
The LSI53C825A IRQ/ output is latched; once asserted, it remains
asserted until the interrupt is cleared by reading the appropriate status
register. Masking an interrupt after the IRQ/ output is asserted does not
cause IRQ/ to be deasserted.
For more information on interrupts, see
Description.”
Registers
R
7
x
MDPE
6
0
Reserved
Master Data Parity Error
Bus Fault
Aborted
Single Step Interrupt
SCRIPTS Interrupt Instruction Received
Reserved
Illegal Instruction Detected
BF
5
0
Interrupt Status (ISTAT)
ABRT
4
0
DMA Status (DSTAT)
SSI
3
0
Chapter 2, “Functional
DMA Status (DSTAT)
SIR
SIP or DIP bit is set.)
Interrupt Status (ISTAT)
2
0
R
1
x
register. An
register.
IID
0
0
7
6
5
4
3
2
1
0