LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 102

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-14
Register: 0x3F
Max_Lat
Read Only
ML
Register: 0x40
Capability ID
Read Only
CID
Registers
7
0
7
0
1
0
Max_Lat
This register is used to specify the desired settings for
latency timer values. Max_Lat is used to specify how
often the device needs to gain access to the PCI bus.
The value specified in these registers is in units of
0.25 microseconds. The LSI53C825A sets this register to
0x40.
Cap_ID
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure. Only the LSI53C825AE
sets this register to 0x01.
0
0
0
0
CID
ML
0
0
0
0
0
0
0
0
0
1
[7:0]
[7:0]