LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 125

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x08 (0x88)
SCSI First Byte Received (SFBR)
Read/Write
IB
Operating Registers
7
0
0
SCSI First Byte Received
This register contains the first byte received in any
asynchronous information transfer phase. For example,
when a LSI53C825A is operating in the initiator mode,
this register contains the first byte received in the
Message-In, Status, and Data-In phases.
When a Block Move instruction is executed for a
particular phase, the first byte received is stored in this
register—even if the present phase is the same as the
last phase. The first byte received value for a particular
input phase is not valid until after a MOVE instruction is
executed.
This register is also the accumulator for register
read-modify-writes with the
(SFBR)
operation.
The
using the CPU, and therefore not by a Memory Move.
However, it can be loaded using SCRIPTS Read/Write
operations. To load the SFBR with a byte stored in
system memory, the byte must first be moved to an
intermediate LSI53C825A register (such as the
SCRATCH register), and then to the SFBR.
This register also contains the state of the lower eight bits
of the SCSI data bus during the Selection phase if the
COM bit in the
SCSI First Byte Received (SFBR)
0
as the destination. This allows bit testing after an
DMA Control (DCNTL)
0
IB
0
SCSI First Byte Received
0
register is clear.
is not writable
0
0
0
[7:0]
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