LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 241

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Table 6.18
6.4 PCI and External Memory Interface Timing Diagrams
Symbol
t
t
t
1
2
3
Parameter
CLK HIGH to IRQ/ LOW
CLK HIGH to IRQ/ HIGH
IRQ/ deassertion time
Interrupt Output
Table 6.18
Figure 6.8
IRQ/
Figure 6.9
LSI53C825A accesses the PCI bus. The timings for the PCI and external
memory buses are listed on
diagrams for access to three groups of external memory configurations.
The first group applies to systems with memory size of 64 Kbytes and
above; one byte read or write cycle, and fast or normal ROMs. The
second group applies to systems with memory size of 64 Kbytes and
above, one byte ready or write cycles, and slow ROMs. The third group
applies to systems with memory size of 64 Kbytes or less, one byte read
or write cycles, and normal or fast ROM.
Timing diagrams included in this section are:
PCI and External Memory Interface Timing Diagrams
CLK
Target Timing
–
Note:
PCI Configuration Register Read
through
and
Interrupt Output
Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
t
2
Figure 6.8
Figure 6.30
provide Interrupt Output timing data.
page
t
3
represent signal activity when the
6-44. This section includes timing
Min
20
40
t
3
1
Max
–
–
–
Unit
CLK
ns
ns
6-13