LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 28

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.2.3 Memory Read Command
2.1.2.4 Memory Write Command
2.1.2.5 Memory Read Multiple Command
2.1.2.6 Memory Read Line Command
2.1.2.7 Memory Write and Invalidate Command
2.1.3 PCI Cache Mode
2.1.3.1 Support for PCI Cache Line Size Register
2-4
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
The Memory Read Multiple command reads data from an agent mapped
in memory address space. All 32 address bits are decoded.
The Memory Read Line command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
The Memory Write and Invalidate command writes data to an agent
when mapped in memory address space. All 32 address bits are
decoded.
The LSI53C825A supports the PCI specification for an 8-bit
Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the
Line Size
Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands.
The LSI53C825A supports the PCI specification for an 8-bit
Size
nonaligned addresses corresponding to cache line boundaries.
Functional Description
register located in PCI configuration space. The
register in PCI configuration space. It can sense and react to
register, the PCI commands Read Line, Read Multiple, and
Cache Line Size
Cache Line
Cache Line
Cache