LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 141

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x1A (0x9A)
Chip Test Two (CTEST2)
Read/Write
DDIR
SIGP
CIO
CM
SRTCH
Operating Registers
DDIR
7
0
Note:
Note:
SIGP
6
0
Bits 4 and 5 may be set if the chip is dual-mapped.
Bits 4 and 5 may be set if the chip is dual-mapped.
Data Transfer Direction
This status bit indicates which direction data is being
transferred. When this bit is set, the data is transferred
from the SCSI bus to the host bus. When this bit is clear,
the data is transferred from the host bus to the SCSI bus.
Signal Process
This bit is a copy of the SIGP bit in the
(ISTAT)
running SCRIPTS instruction. When this register is read,
the SIGP bit in the ISTAT0 register is cleared.
Configured as I/O
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
Configured as Memory
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
SCRATCHA/B Operation
This bit controls the operation of the
(SCRATCHA)
registers. When it is set, SCRATCHB contains the RAM
base address value from the PCI configuration RAM
Base Address register. This is the base address for the
4 Kbyte internal RAM. In addition, the
(SCRATCHA)
based address of the chip operating registers. When this
CIO
5
x
register (bit 5). The SIGP bit is used to signal a
and
register displays the memory-mapped
CM
4
x
Scratch Register B (SCRATCHB)
SRTCH
3
0
TEOP
2
0
Scratch Register A
Scratch Register A
Interrupt Status
DREQ
1
0
DACK
0
1
4-53
7
6
5
4
3