LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 33

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.3.7 Memory Read Multiple Command
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C825A supports PCI Read
Multiple functionality and issues Read Multiple commands on the PCI
bus when the Read Multiple Mode is enabled. This mode is enabled by
setting bit 2 of the
is enabled, a Read Multiple command is issued on all read cycles, except
opcode fetches, when the following conditions are met:
When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to be read is a multiple of the cache line size as allowed for in the
Revision 2.1 of the PCI specification. The logic selects the largest
multiple of the cache line size based on the amount of data to transfer,
with the maximum allowable burst size determined from the DMODE
burst size bits and
PCI Addressing
The number of bytes to be transferred at the time a cache boundary
is reached is equal to or greater than the DMODE burst size.
The chip is aligned to a cache line boundary.
The CLSE and ERMP bits are set.
The
Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMODE burst size.
The number of bytes to be transferred at the time a cache line
boundary has been reached must be at least twice the full cache line
size.
The chip is aligned to a cache line boundary.
Cache Line Size
DMA Mode (DMODE)
Chip Test Five
register contains a legal burst size value in
(CTEST5), bit 2.
register (ERMP). If cache mode
2-9