LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 157

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x3A (0xBA)
Scratch Byte Register (SBR)
Read/Write
SBR
Register: 0x3B (0xBB)
DMA Control (DCNTL)
Read/Write
CLSE
PFF
PFEN
Operating Registers
CLSE
7
0
7
0
PFF
6
0
0
Scratch Byte Register
This is a general purpose register. Apart from CPU
access, only register read/write and memory moves into
this register alter its contents. The default value of this
register is zero. This register is called the DMA Watchdog
Timer on previous LSI53C8XX family products.
Cache Line Size Enable
Setting this bit enables the LSI53C825A to sense and
react to cache line boundaries set up by the
(DMODE)
contains the smaller value. Clearing this bit disables the
cache line size logic and the LSI53C825A monitors the
cache line size using the
Prefetch Flush
Setting this bit causes the prefetch unit to flush its
contents. This bit clears after the flush is complete.
Prefetch Enable
Setting this bit enables the prefetch unit if the burst size
is equal to or greater than four. For more information on
SCRIPTS instruction prefetching, see
tional Description.”
PFEN
5
0
0
or PCI
SSM
4
0
0
Cache Line Size
SBR
IRQM
3
0
0
DMA Mode (DMODE)
STD
0
2
0
register, whichever
Chapter 2, “Func-
IRQD
0
1
0
DMA Mode
register.
COM
0
0
0
0
[7:0]
4-69
7
6
5