LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 148

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-60
DFS
MASR
DDIR
BL2
BO[9:8]
Registers
clears itself after decrementing the
(DBC)
DMA FIFO Size
This bit controls the size of the DMA FIFO. When clear,
the DMA FIFO appears as only 88 bytes deep. When set,
the DMA FIFO size increases to 536 bytes. Using an
88-byte FIFO allows software written for other
LSI53C8XX family chips to properly calculate the number
of bytes residing in the chip after a target disconnect. The
default value of this bit is zero.
Master Control for Set or Reset Pulses
This bit controls the operation of bit 3. When this bit is
set, bit 3 asserts the corresponding signals. When this bit
is cleared, bit 3 deasserts the corresponding signals. Do
not change this bit and bit 3 in the same write cycle.
DMA Direction
Setting this bit either asserts or deasserts the internal
DMA Write (DMAWR) direction signal depending on the
current status of the MASR bit in this register. Asserting
the DMAWR signal indicates that data is transferred from
the SCSI bus to the host bus. Deasserting the DMAWR
signal transfers data from the host bus to the SCSI bus.
Burst Length Bit 2
This bit works with bits 6 and 7 (BL[1:0]) in the
Mode
burst length. For complete definitions of this field, refer to
the descriptions of
This bit is disabled if an 88-byte FIFO is selected by
clearing the DMA FIFO Size bit.
DMA FIFO Byte Offset Counter, Bits [9:8]
These are the upper two bits of the DFBOC. The DFBOC
consists of these bits and the
bits [7:0].
(DMODE),
register.
0x38 (0xB8)
DMA Mode
DMA FIFO (DFIFO),
register to determine the
(DMODE), bits 6 and 7.
DMA Byte Counter
DMA
[1:0]
5
4
3
2