LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 124

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Instruction. GPIO[3:0] default as inputs and GPIO4
defaults as an output pin. When configured as inputs, an
internal pull-down is enabled.
GPIO4 can be used to enable or disable V
, the 12 V
PP
power supply to the external flash memory. This bit
powers up with the power to the external memory
disabled.
The GPIO[1:0] signals can also be controlled from PCI
configuration register 0x35. They may be read, but not
controlled, from this register.
LSI Logic software uses GPIO3 to detect a differential
board. If the pin is pulled low externally, the board will be
configured by SDMS software as a differential board. If it
is pulled high or left floating, SDMS software will
configure it as an SE board. The LSI Logic PCI to SCSI
host adapters use the GPIO4 pin in the process of
flashing a new SDMS software ROM.
LSI Logic software uses the GPIO0 pin to toggle SCSI
device LEDs, turning on the LED whenever the
LSI53C825A is on the SCSI bus. SDMS software drives
this pin low to turn on the LED, or drives it high to turn
off the LED.
SDMS software uses the GPIO[1:0] pins to support serial
EEPROM access. When serial EEPROM access is
enabled, GPIO1 is used as a clock and GPIO0 is used
as data. The pins are controlled from PCI configuration
register 0x35. They may be read, but not controlled, from
this register.
4-36
Registers