LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 100

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-12
Register: 0x34
Capability Pointer
Read Only
CP
Registers
7
0
1
The Expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit is used to control whether
or not the device accepts accesses to its expansion
ROM. When the bit is set, address decoding is enabled,
and a device can be used with or without an expansion
ROM depending on the system configuration. To access
the external memory interface, the Memory Space bit in
the
The host system detects the size of the external memory
by first writing the
with all ones and then reading back the register. The
LSI53C825A will respond with zeros in all don’t care
locations. The ones in the remaining bits represent the
binary version of the external memory size. For example,
to indicate an external memory size of 32 Kbytes, this
register, when written with ones and read back, will return
ones in the upper 17 bits.
Capabilities Pointer
This register provides an offset into the function’s PCI
Configuration Space for the location of the first item in the
capabilities linked list. Only the LSI53C825AE sets this
register to 0x40. The capability pointer replaces the
General Purpose Pin Control register in earlier revisions
of the LSI53C825A.
Command
0
register must also be set.
0
Expansion ROM Base Address
CP
0
0
0
register
0
0
[7:0]