LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 147

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

FBL[2:0]
Register: 0x22 (0xA2)
Chip Test Five (CTEST5)
Read/Write
ADCK
BBCK
Operating Registers
ADCK
7
0
BBCK
6
0
FIFO Byte Control
These bits steer the contents of the
(CTEST6)
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2
through FBL0 determine which of eight byte lanes can be
read or written. When cleared, the byte lane read or
written is determined by the current contents of the
Next Address (DNAD)
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
Clock Address Incrementor
Setting this bit increments the address pointer contained
in the
Next Address (DNAD)
the DNAD contents and the current
(DBC)
incrementing the
Clock Byte Counter
Setting this bit decrements the byte count contained in
the 24-bit
decremented based on the DBC contents and the current
DMA Next Address (DNAD)
FBL3
0
1
1
1
1
DFS
DMA Next Address (DNAD)
5
0
value. This bit automatically clears itself after
FBL2
DMA Byte Counter (DBC)
register to the appropriate byte lane of the
0
0
0
0
x
MASR
4
0
DMA Next Address (DNAD)
FBL1
x
0
0
1
1
and
register is incremented based on
DDIR
3
0
FBL0
DMA Byte Counter (DBC)
x
0
1
0
1
value. This bit automatically
BL2
DMA FIFO
Byte Lane
2
x
Disabled
register. The
DMA Byte Counter
Chip Test Six
register. It is
0
1
2
3
1
x
BO[9:8]
register.
D[23:16]
D[31:24]
D[15:8]
D[7:0]
DMA
Pins
N/A
DMA
0
x
[2:0]
4-59
7
6