LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 32

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.3.6 Memory Read Line Command
2-8
PCI Target Retry – During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was
transferred), the chip relinquishes the bus and immediately tries to finish
the transfer on another bus ownership. The chip issues another Write
and Invalidate command on the next ownership, in accordance with the
PCI specification.
PCI Target Disconnect – During a Write and Invalidate transfer, if the
target device issues a disconnect the LSI53C825A relinquishes the bus
and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Write and Invalidate command on the
next ownership unless the address is aligned.
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading up to a cache line boundary rather
than a single memory cycle. The Read Line Mode function that exists in
the previous LSI53C8XX chips has been modified in the LSI53C825A to
reflect the PCI
of the Enable Read Line bit (bit 3 in
modified to more resemble the Write and Invalidate mode in terms of
conditions that must be met before a Read Line command is issued.
However, the Read Line option operates exactly like the previous
LSI53C8XX chips when cache mode is disabled by a CLSE bit reset or
when certain conditions exist in the chip (explained below).
The Read Line mode is enabled by setting bit 3 in the
(DMODE)
issued on every read data transfer, except opcode fetches, as in previous
LSI53C8XX chips.
If cache mode is enabled, a Read Line command is issued on all read
cycles, except opcode fetches, when the following conditions are met:
Functional Description
The CLSE and Enable Read Line bits are set.
The
Dwords (2, 4, 8, 16, 32, 64, or 128) that value is less than or equal
to the DMODE burst size.
Cache Line Size
register. If cache mode is disabled, Read Line commands are
Cache Line Size
register contains a legal burst size value in
register specifications. The functionality
DMA Mode
(DMODE)) has been
DMA Mode