LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 168

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

4-80
Register: 0x46 (0xC6)
Memory Access Control (MACNTL)
Read/Write
TYP[3:0]
DWR
DRD
PSCPT
SCPTS
Registers
7
0
1
TYP[3:0]
Wide Residue message is received. It may also be an
overrun data byte. The power-up value of this register is
indeterminate.
Chip Type
These bits identify the chip type for software purposes.
This technical manual applies to devices that have these
bits set to 0x06.
Bits 3 through 0 of this register are used to determine if
an external bus master access is to local or far memory.
When bits 3 through 0 are set, the corresponding access
is considered local and the MAC/_TESTOUT pin is driven
high. When these bits are clear, the corresponding
access is to far memory and the MAC/_TESTOUT pin is
driven low. This function is enabled after a Transfer
Control SCRIPTS instruction is executed.
DataWR
This bit is used to define if a data write is considered
local memory access.
DataRD
This bit is used to define if data write is considered local
memory access.
Pointer SCRIPTS
This bit is used to define if a pointer to a SCRIPTS
indirect or table indirect fetch is considered local memory
access.
SCRIPTS
This bit is used to define if a SCRIPTS fetch is
considered local memory access.
1
4
0
DWR
3
0
DRD
2
0
PSCPT
1
0
SCPTS
0
0
[7:4]
3
2
1
0